The present invention relates to semiconductor devices, and in particular to conductive path layers for such devices.
A conventional semiconductor device, in this case a field-effect transistor, is shown in FIG. 1. The illustrated structure includes a substrate 1000, of silicon for example, in which are formed a low density impurity (i.e. lightly doped) diffused region 1001 and a high density impurity (i.e. heavily doped) diffused region 1002, these regions forming source and drain regions of the transistor. An oxide film region 1003 is disposed on substrate 1000 and a gate electrode 1004 is disposed on oxide film region 1003. Gate electrode 1004 and region 1003 are surrounded by a sidewall layer 1005 and the transistor is surrounded and isolated by an insulating layer 1006. An interlayer insulating film 1007 is disposed above layer 1006 as well as regions 1001 and 1002 and electrode 1004.
Aluminum wiring paths 1008 are connected to regions 1001 and 1002. Wiring paths 1008 and film 1007 are covered by a passivation layer 1009.
As commonly occurs in conventional manufacturing processes, the structure contains various flaws, such as a protrusion 1010 or a void 1011 on aluminum path 1008 and/or a void 1012 in passivation layer 1009.
As mentioned above, in conventional semiconductor devices, the single-layer wiring 1008 composed of Al or Al-Si (1%) and so on is formed by the methods of sputtering, vapor deposition, etc.
FIGS. 2a and 2b illustrate successive stages in one conventional semiconductor device manufacturing process. In FIG. 2a, a semiconductor substrate 1101 has a semiconductor device region which is surrounded by an isolating insulating layer 1102. To form the semiconductor device, a gate insulating film 1103 is formed on substrate 1101 and a gate electrode 1104 is then formed on film 1103. Electrode 1104 may be a polycide, i.e. two layers of polysilicon and metal silicide having a high melting point. At opposite sides of electrode 1104, a low density impurity .region 1105 and a high density impurity region 1107 are diffused into substrate 1101, these constituting source and drain regions. A sidewall film 1106 is formed around electrode 1104 and film 1103. Then, an insulating layer 1108 is deposited on layer 1102, electrode 1104, film 1106 and regions 1105 and 1107. Openings are formed in layer 1108 and a first layer of conductive regions 1109 is deposited on layer 1108 and in the openings formed in that layer to form contacts to regions 1105 and 1107. Conductive regions 1109 are composed of Al or Al-Si. Regions 1109 may be produced by sputtering.
Then, as shown in FIG. 2b, a further insulating layer 1112 is deposited on regions 1109 and the exposed parts of layer 1108, followed by a second layer 1113 of conductive regions, which are connected to regions of layer 1109 via openings formed in layer 1112. Then a further insulating layer 1118 is formed on regions 1113 and the exposed parts of layer 1112.
The conductive layers are formed by thermal sputtering and photoetching.
Thermal sputtering constitutes an effective method for depositing conductive layer 1109, for example of Al, on insulating layer 1108 and the exposed regions of substrate 1101 so that no spaces exist between layer 1109 and the underlying surfaces. Thus, this technique exhibits a good "throwing power", which denotes the degree to which the applied layer fills all underlying spaces, for the extent to which it covers the underlying surfaces.
During the subsequent heating process, projections such as shown at 1116 grow. These projections promote current leakage between insulating layers. Voids, or recesses, 1117 may also form in the conductive regions.
FIGS. 3a, b and c show three stages in the manufacture of another conventional semiconductor device. Every part shown in FIG. 3a corresponds to the part whose reference numeral has the same last two digits in FIG. 2a.
After openings are formed in layer 1208, a conductive metal pattern 1211 is deposited on layer 1208 and in the openings previously formed in that layer. Then metal 1211 and the exposed parts of layer 1208 are covered by a further insulating layer 1212.
Then, referring to FIG. 3c, an opening is formed in layer 1212 to expose metal 1211. A Cr layer 1221 and an Au layer 1222 are then deposited in the opening for the plating electrode. Photoetching is performed with the aid of a mask having the shape 1223. Then Au plating 1225 is performed through a resist mask 1224. The AU plating 1225 forms a bump, or button, electrode which constitutes an external connector for conducting an input or output current of the semiconductor device.
With conventional methods, a conductive layer, for example of Al, cannot be formed on the lower insulating layer and the conductive layer then be exposed by a contact opening so as to leave no space between the Al layer and the underlying insulating layer or the conductive layer cannot be exposed by a very small passage opening having a high aspect ratio. In addition, although known structures do not necessarily result in a burnout, or a broken conductor, initially, the reliability of known structures of this type is very low.
With conventional manufacturing processes, as shown in FIGS. 1 and 3b, cracks and voids 1012, 1220 are formed in passivation layer 1009, 1212. These cracks and voids adversely influence the moisture resistance of the semiconductor device.
Further, low melting point aluminum alloys develop protrusions such as 1010, 1116 and voids such as 1011, 1012, 1117, 1219 during the thermal process, and promote penetration of aluminum into shallow diffused regions, junction spikes, etc.
By contacting the Al alloy and Si substrate directly, the deposited Si layer is formed at the interface, thereby producing a step contact resistance and variations in the contact resistance. In particular, in devices having dimensions in the submicron range, the above undesirable characteristics become particularly troublesome. In fact the prior art has reached a lower size limit for such devices for achieving satisfactory reliability.
Furthermore, with conventional Al conductive paths, it is impossible to prevent stress migration, in which strong tensile stress remains in the conductive paths, associated with compressive stress in the adjacent passivation layer, thereby resulting in a creep diffusion phenomenon which causes burnout of the conductive paths.
Moreover, electrode migration has already reached the limit of device reliability and conductive path material having high reliability is needed to allow a stable flow of high current levels.
According to the conventional art, when the interlayer insulating film 1112 is formed as in FIG. 2(b), a projection 1116 grows into the surface and side of conductive layer 1109, whereupon a current short may form between the first conductive layer 1109 and the second conductive layer 1113. And, if a compressive plasma nitride layer or the like is used as the passivation layer 1118, the void 1117 due to stress migration occurs in Al layer 1113. Further, there occurs burnout and deterioration of the electron migration resistance. Where the conductive layer is not heated, less of a projection is produced. However, the throwing power at the contact portion becomes poor, and the stress migration becomes weak.
Further, according to the conventional art, when the contact openings in the insulating layer, e.g. layer 1108, are small and the aspect ratio of the layer is large, the coverage at the contact portion by the conductive material becomes poor. In particular, at the time of non-heating the crack 1219 occurs as shown in FIG. 3b. Further burnout occurs and the electro or stress migration resistance also deteriorates. The worse the coverage of the conductive portion, the worse the throwing power of the passivation layer at the top of the structure. Thereby, the occurrence of voids like 1220 substantially reduce the moisture resistance of the device.